RESPONSIBILITIES:

📍Bring up, validate and characterize high speed SerDes blocks in new and existing silicon chips 📍Develop test methods to evaluate performance and calculate operating margins of high-speed serial interfaces (SerDes) across PVT and additional environmental conditions specific to space applications 📍Work closely with the ASIC design team to add/improve testability and define various loopback and test infrastructure logic to ensure adequate silicon test coverage 📍Work closely with electrical design team to review signal integrity, power integrity and radiated/conducted emissions concerns as well as propose design changes or operational workarounds 📍Evaluate new SerDes IP from internal and external IP providers and test for logical and electrical compatibility with existing chips and FPGAs 📍Write software routines (Python, C/C++) to bring up and validate the SerDes while working with the software cross functional team members to help integrate SerDes drivers in the software track

BASIC QUALIFICATIONS:

📍Master's degree in electrical engineering, computer engineering or computer science 📍5+ years of professional experience working on SerDes platforms

PREFERRED SKILLS AND EXPERIENCE:

📍Experience working with various high speed SerDes architectures (NRZ, PAM4) and protocols 📍Working knowledge of Serdes block, e.g. CTLE, DFE, FFE, CDR and PLLs, their characterization and debug. 📍Very good working knowledge of test and measurement equipment such as high-speed Oscillators, BERTs 📍Understanding of SerDes calibration, including how equalization parameters are chosen 📍Working knowledge of SerDes Signal Integrity eye diagrams, Bathtub Curves, etc. 📍Working experience with ethernet, PCIe and other high-speed protocol layers is a definite plus 📍Ability to study and analyze internal and external resources to lead SerDes IP selections and discussions 📍Experience writing comprehensive test reports covering test boundary conditions and test results 📍Strong debugging and problem-solving skills